1. Field of the Invention
Embodiments of the invention relate to a liquid crystal display device, and more particularly, to a liquid crystal display (LCD) device and a method of fabricating the same.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, many efforts are being made to study and develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays, and electro-luminescence displays (ELDs), as a substitute for CRTs. Of these flat panel displays, the LCD devices have many advantages, such as high resolution, light weight, thin profile, compact size, and low voltage power supply requirements.
In general, an LCD device includes two substrates that are spaced apart and face each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes in accordance with the intensity of the induced electric field into direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
FIG. 1 is a perspective view illustrating an LCD device according to the related art. Referring to FIG. 1, the LCD device 51 includes an array substrate, a color filter substrate and a liquid crystal layer between the two substrates. The color filter substrate includes a black matrix 6, and red (R), green (G) and blue (B) color filter patterns 7a, 7b and 7c on a second substrate 5. A common electrode 9 is disposed on the color filter patterns 7a, 7b and 7c. The array substrate includes a gate line 14 and a data line 26 crossing each other on a first substrate 10 to define a pixel region P. A thin film transistor T is disposed near a crossing portion of the gate and data lines 14 and 26. A pixel electrode 32 is disposed in the pixel region P and connected to the thin film transistor T.
The array substrate is fabricated with five mask processes. A gate electrode and the gate line are formed in a first mask process. A semiconductor layer is formed in a second mask process. A data line, a source electrode and a drain electrode are formed in a third mask process. A passivation layer having a contact hole exposing the drain electrode is formed in a fourth mask process. A pixel electrode is formed in a fifth mask process.
Because the array substrate is fabricated with the five mask processes, fabrication time is long and product cost is high. To resolve these problems, a method of fabricating an array substrate with four mask processes has been suggested. One less mask process reduces both fabrication time and product cost.
FIG. 2 is a plan view illustrating an array substrate for an LCD device fabricated with four mask processes according to the related art. Referring to FIG. 2, a gate line 62 and a data line 98 cross each other on a substrate to define a pixel region. A gate pad electrode 64 is disposed at one end of the gate line 62, and a data pad electrode 100 is disposed at one end of the data line 98. A gate pad electrode terminal 114 is disposed on the gate pad electrode 64, and a data pad electrode terminal 116 is disposed on the data pad electrode 100.
A thin film transistor T is disposed near a crossing of the gate and data lines 62 and 98. The thin film transistor T includes a gate electrode 64, a first semiconductor layer 90a, and source and drain electrodes 94 and 96. A pixel electrode 112 is disposed in the pixel region and contacts the drain electrode 96.
A storage electrode 86 overlaps the gate line 62. The storage electrode 86, the gate line 62 and a gate insulating layer therebetween form a storage capacitor Cst. A second semiconductor layer 90b is disposed below the data line 98, and a third semiconductor layer 90c is disposed below the storage electrode 86.
Because metal patterns, such as the data line 98, the storage electrode 86 and the source and drain electrodes 94 and 96, and the semiconductor patterns, such as the first to third semiconductor layers 90a to 90c are formed in the same mask process, the semiconductor patterns are disposed below the metal pattern. A part of the first semiconductor layer 90a extends outside of the gate electrode 64. The extended part of the first semiconductor layer 90a is exposed to a backlight and activated.
FIG. 3 is a cross-sectional view illustrating a thin film transistor of FIG. 2. Referring to FIG. 3, a first semiconductor layer 90a includes an active layer 92a and an ohmic contact layer 92b of amorphous silicon. Because the first semiconductor layer 90a is formed along with source and drain electrodes 94 and 96, the first semiconductor layer 90a has substantially the same outline as the source and drain electrodes 94 and 96. Accordingly, a part of the first semiconductor layer 90a extends outside a gate electrode 62. The extended part of the first semiconductor layer 90a is exposed to a backlight, and thus a leakage current can occur. The leakage current causes a voltage charged in a pixel region to abnormally leak through the thin film transistor T. Accordingly, characteristics of the thin film transistor T are degraded. This is a problem in the four mask processes according to the related art.
When amorphous silicon is used for the semiconductor layer, an inverted staggered type thin film transistor like the thin film transistor of FIG. 3 is formed. In the inverted staggered type thin film transistor T, a channel CH of the thin film transistor T is exposed to an exterior circumstance before forming a passivation layer 100. Accordingly, the channel CH may have defect or contamination during the subsequent processes. These are other problems of the four mask processes according to the related art. Such a defect or contamination can also cause leakage current in the thin film transistor.
FIGS. 4A to 4F, 5A to 5F and 6A to 6F are cross-sectional views, taken along lines II-II, III-III and IV-IV of FIG. 2, illustrating a method of fabricating an array substrate for an LCD device with four mask processes according to the related art. Referring to FIGS. 4A, 5A and 6A, a metallic material is deposited on a substrate 60 having a pixel region P, a switching region S, a gate region G, a data region D and a storage region C. The metallic material layer is patterned with a first mask process to form a gate line 62, a gate pad electrode 66 and a gate electrode 64.
Referring to FIGS. 4B, 5B and 6B, a gate insulating layer 68, an intrinsic amorphous silicon layer 70, an impurity-doped amorphous silicon layer 72 and a metallic material layer 74 are formed on the substrate 60 having the gate line 62. A photoresist layer is formed on the metallic material layer 74. The photoresist layer is patterned with a second mask to form first to third photoresist patterns 78a to 78c in the switching region S, the data region D and the storage region S. A portion of the first photoresist pattern 78a corresponding to the gate electrode 64 has a thinner thickness than other portions. The metallic material layer 74, the impurity-doped amorphous silicon layer 72 and the intrinsic amorphous silicon layer 70 are patterned with the first to third photoresist patterns 78a to 78c. 
Referring to FIGS. 4C, 5C and 6C, first to third metal patterns 80, 82 and 86 are formed below the first to third photoresist patterns 78a to 78c. First to third semiconductor layers 90a to 90c are formed below the first to third metal patterns 80, 82 and 86. An ashing process is performed on the first to third photoresist patterns 78a to 78c to remove the thinner portion of the first photoresist pattern 78a. As a result of the ashing process, the sides of the first to third photoresist patterns 78a to 78c are also removed. The first to third metal patterns 80, 82 and 86 and the impurity-doped amorphous silicon layers 72 of the first to third semiconductor layers 90a to 90c are patterned with the ashed first to third photoresist patterns 78a to 78c. 
Referring to FIGS. 4D, 5D and 6D, source and drain electrodes 94 and 96, a data line 98 and a data pad electrode 100 are formed. The third metal pattern 86 is referred to as a storage electrode 86. The impurity-doped amorphous silicon layer 72 of the first semiconductor layer 90a is referred to as an ohmic contact layer 92b, and the intrinsic amorphous silicon layer 70 of the first semiconductor layer 90a is referred to as an active layer 92a. The storage electrode 86 forms a storage capacitor Cst with the gate line 62.
Referring to FIGS. 4E, 5E, and 6E, a passivation layer 102 is formed on the substrate 60 having the data line 98. The passivation layer 102 is patterned with a third mask process to form a drain contact hole 104 exposing the drain electrode 96, a storage contact hole 106 exposing the storage electrode 86, and a data pad contact hole 110 exposing the data pad electrode 100. Also, the passivation layer 102 and the gate insulating layer 68 are patterned with the third mask process to form a gate pad contact hole 108 exposing the gate pad electrode 66.
Referring to FIGS. 4F, 5F and 6F, a transparent conductive material is deposited on the passivation layer 102 and patterned with a fourth mask process to form a pixel electrode 112, a gate pad electrode terminal 114 and a data pad electrode terminal 116. The pixel electrode 112 contacts the drain electrode 96 through the drain contact hole 104 and the storage electrode 86 through the storage contact hole 106. The gate pad electrode terminal 114 contacts the gate pad electrode 66 through the gate pad contact hole 108, and the data pad electrode terminal 116 contacts the data pad electrode 100 through the data pad contact hole 110.
Through the above four mask processes, the array substrate is fabricated. As explained above, the channel of the active layer may be contaminated or have defect because the passivation layer is formed after the formation of the channel. Also, the active layer is not within an area defined by the gate electrode and exposed to a backlight because the active layer is formed in the same mask process as the source and drain electrodes. Accordingly, a leakage current may occur that degrades display quality. Further, the thin film transistor occupies a part of the pixel region, and thus aperture ratio is reduced.